Back to all jobs
Cisco
ASIC Engineering Technical Leader | RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) | Exp - 12+ years
Bangalore, IndiaFull-timeDirect from Cisco
This role is no longer active — it's been removed from Cisco's careers site and is no longer accepting applications.
ASIC Engineering Technical Leader | RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) | Exp - 12+ years
Full description, salary range & apply link — for members.
Free account · 10-second signup · no credit card.
Already have an account? Sign in