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ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)
Pune, IndiaFull-timeDirect from Cisco
This role is no longer active — it's been removed from Cisco's careers site and is no longer accepting applications.
ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)
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